Figure 6 shows the field
emission measurements for CoSi NWs. Figure 6a is the plot of the current density (J) as a function of the applied field (E) with the inset of the ln(J/E 2) − 1/E plot. The sample was measured in a vacuum chamber pump to approximately 10−6 Torr. According to the Fowler-Nordheim plot and the Fowler-Nordheim equation: where J is the current density, E is the applied electric field, and φ is the work function; for CoSi, φ is 4.7 eV. A and B are constants, corresponding to 1.56 × 10−10 (A (eV)/V −2) and 6.83 × 109 (V (eV)−3/2 m−1), respectively. The field enhancement ß has been calculated to be 1,384 from the slope of ln(J/E 2) = ln(Aß 2/φ) − Bφ 3/2/ßE, proving that CoSi NWs are promising emitters. Also, the higher the density of CoSi NWs, the better the field emission property as shown in Figure 6b. The outstanding field emission properties of CoSi NWs are attributed to their metallic property and special Defactinib nmr one-dimensional geometry. Figure 6 Field emission analysis. (a) The field emission plot of CoSi NWs.
The inset in (a) shows the corresponding ln(J/E 2) − 1/E plot. (b) The field emission plot of CoSi NWs with different densities. Conclusions In this study, using a CVD method, we have synthesized cobalt silicide nanowires of two different phases, which are CoSi NWs and Co2Si NWs, respectively. Effects of some processing parameters, including the temperature, gas flow rate, and pressure, were investigated; for example, the number of CoSi nanowires shows a decreasing JQEZ5 mw trend with the increasing gas flow rate. Also, the growth mechanism has been proposed. Electrical measurements demonstrate that the CoSi nanowires are potential field-emitting materials. Selleckchem GDC-973 Acknowledgment KCL acknowledges the support from the National Science Council through grant 100-2628-E-006-025-MY2. References 1. Zhang SL, Ostling M: Metal silicides in CMOS technology: past, Nabilone present, and future trends. Crit Rev Solid State Mat Sci 2003, 28:1–129.CrossRef 2. Chen LJ: Silicide Technology for Integrated Circuits. London: The Institution of Electrical Engineers;
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